sed1374 ETC-unknow, sed1374 Datasheet - Page 30

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Page 22
5.3 Summary of Configuration Options
5.4 Host Bus Interface Pin Mapping
SED1374
X26A-A-001-02
Pin Names
Configuration
SED1374
DB[15:0]
RD/WR#
RESET#
AB[15:1]
WAIT#
WE1#
WE0#
BCLK
CNF[2:0]
AB0
CS#
BS#
RD#
CNF4
CNF3
Pin
RD/WR#
RESET#
D[15:0]
Active high (On) LCDPWR polarity
Big Endian
Select host bus interface as follows:
A[15:1]
WAIT#
WE1#
WE0#
CSn#
CKIO
SH-3
RD#
BS#
A0
CNF2
0
0
0
0
1
1
1
1
1
1
Table 5-1: Summary of Power On/Reset Options
RD/WR#
RESET#
A[15:1]
D[15:0]
WE1#
WE0#
RDY#
CSn#
CKIO
SH-4
RD#
BS#
Table 5-2: Host Bus Interface Pin Mapping
A0
CNF1
0
0
1
1
0
0
1
1
1
1
1
CNF0
connect to IO V
connect to IO V
0
1
0
1
0
1
0
0
1
1
External Decode External Decode External Decode
MC68K #1
DTACK#
RESET#
A[15:1]
D[15:0]
UDS#
LDS#
R/W#
CLK
AS#
BS#
X
X
X
X
X
X
0
1
0
1
Power On/Reset State
DD
DD
Host Bus
SH-4 interface
SH-3 interface
reserved
MC68K #1, 16-bit
reserved
MC68K #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
Active low (On) LCDPWR polarity
Little Endian
MC68K #2
DSACK1#
RESET#
D[31:16]
A[15:1]
R/W#
SIZ1
SIZ0
DS#
CLK
AS#
A0
connect to V
Generic #1
RESET#
Epson Research and Development
A[15:1]
D[15:0]
WAIT#
WE1#
BCLK
WE0#
RD1#
RD0#
Hardware Functional Specification
A0
0
SS
Vancouver Design Center
connect to IO V
connect to IO V
Issue Date: 99/04/29
External Decode
Generic #2
RESET#
A[15:1]
D[15:0]
WAIT#
BHE#
BCLK
WE#
RD#
A0
DD
DD

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