pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 438

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

COFA Event Counter (Read)
COE(7:2)
COE(1:0)
User’s Manual
Hardware Description
Multiframe Counter
If GCR.ECMC = 1 this 6 bit counter increments with each multiframe
period in the asynchronous state FRS0.LFA/LMFA = 1. The error
counter does not roll over.
Change of Frame Alignment Counter
If GCR.ECMC = 1 this 2 bit counter increments with each detected
change of frame/multiframe alignment. The error counter does not roll
over.
During alarm simulation, the counter is incremented once per
multiframe.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the event counter bit DEC.DCOEC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCOEC is
automatically reset with reading the error counter high byte on
address 5B
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
H
. Data read on 5B
438
H
is not defined.
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56