pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 138

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

5.1.15
The signaling controller can be programmed to operate in various signaling modes. The
FALC
5.1.15.1 HDLC or LAPD Access
The FALC
attached either to the line side ("normal HDLC") or to the system side ("inverse HDLC").
Each of them provides the following features:
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In addition to this, HDLC channel 1 provides:
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In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD
according to Q.921 is supported. The signaling controller of the FALC
flag detection, CRC checking, address comparison and zero bit removing. The received
data flow and the address recognition features can be performed in very flexible way, to
satisfy almost any practical requirements. Depending on the selected address mode, the
FALC
selected, the high address byte is compared with the fixed value FEH or FCH (group
address) as well as with two individually programmable values in RAH1 and RAH2
registers. According to the ISDN LAPD protocol, bit 1 of the high byte address is
interpreted as command/response bit (C/R) and is excluded from the address
comparison. Buffering of receive data is done in a 64 byte deep RFIFO.
In signaling controller transparent mode, fully transparent data reception without HDLC
framing is performed, i.e. without flag recognition, CRC checking or bit stuffing. This
allows user specific protocol variations.
User’s Manual
Hardware Description
64 byte receive FIFO for each channel
64 byte transmit FIFO for each channel
Transmission in one of 24 time slots
(time slot number programmable for each channel individually)
Transmission in even frames only, odd frames only or both
(programmable for each channel individually)
Bit positions to be used in selected time slots are maskable
(any bit position can be enabled for each channel individually)
HDLC or transparent mode
Flag detection
CRC checking
Bit-stuffing
Flexible address recognition (1 byte, 2 bytes)
C/R bit processing (according to LAPD protocol)
SS7 support
BOM (bit oriented message) support
Flexibility to insert and extract data during certain time slots, any combination of time
slots can be programmed independently for the receive and transmit direction
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®
56 performs the following signaling and data link methods.
56 performs a 1 or 2-byte address recognition. If a 2-byte address field is
®
Receive Signaling Controller (T1/J1)
56 offers three independent HDLC channels. Any HDLC channel can be
138
Functional Description T1/J1
®
DS1.1, 2003-10-23
PEF 2256 H/E
56 performs the
FALC
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56