pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 167

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Figure 57
5.4.7
Similar to the receive signaling controller the same signaling methods and the same time
slot assignment are provided. The FALC
link methods.
5.4.7.1
The transmit signaling controller of the FALC
generation, zero bit stuffing and programmable idle code generation. Buffering of
transmit data is done in the 64 byte deep XFIFO. The signaling information is internally
multiplexed with the data applied to port XDI or XSIG.
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the FALC
transmission of the XFIFO contents.
Operating in HDLC or BOM mode “flags” or “idle” are transmitted as interframe timefill.
The FALC
combinations of time slots can be programmed separately for the receive and transmit
direction if using HDLC channel 1. HDLC channel 2 and 3 support one programmable
time slot common for receive and transmit direction each.
5.4.7.2
The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is
described in ITU-Q.703. The following description assumes, that the reader is familiar
with the SS7 protocol definition.
User’s Manual
Hardware Description
®
Transmit Signaling Controller (T1/J1)
HDLC or LAPD access
Support of Signaling System #7
56 offers the flexibility to insert data during certain time slots. Any
Transmit Line Monitor Configuration (T1/J1)
XL1
XL2
®
167
Monitor
56 performs the following signaling and data
Line
TRI
®
56 performs the flag generation, CRC
®
Functional Description T1/J1
Shaper
56 supports the continuous
Pulse
XDATA
ITS10936
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56