pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 327

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

XLSC
XPR
Interrupt Status Register 2 (Read)
ISR2
All bits are reset when ISR2 is read.
If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are masked by
register IMR2. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
FAR
LFA
MFAR
User’s Manual
Hardware Description
FAR
7
Transmit Line Status Change
XLSC is set with the rising edge of the bit FRS1.XLO or with any
change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
Transmit Pool Ready - HDLC Channel 1
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Frame Alignment Recovery
The framer has reached doubleframe synchronization. Set when bit
FRS0.LFA is reset. It is set also after alarm simulation is finished and
the receiver is still synchronous.
Loss of Frame Alignment
The framer has lost synchronization and bit FRS0.LFA is set. It is set
during alarm simulation.
Multiframe Alignment Recovery
Set when the framer has found two CRC-multiframes at an interval of
n × 2 ms (n = 1, 2, 3, and so forth) without a framing error. At the
same time bit FRS0.LMFA is reset.
It is set also after alarm simulation is finished and the receiver is still
synchronous. Only active if CRC-multiframe format is selected.
LFA
MFAR
T400MS
327
AIS
LOS
RAR
DS1.1, 2003-10-23
PEF 2256 H/E
RA
E1 Registers
0
FALC
(6A)
®
56