pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 41

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 4
Pin or
Ball No.
67 (D6)
68 (A6)
69 (B5)
70 (D5)
User’s Manual
Hardware Description
Name
RPA
RPB
RBC
RPD
Pin Definitions - System Interface (cont’d)
Pin
Type
O
O
O
O
Buffer
Type
Function
Receive Signaling Marker (RSIGM)
PC(1:4).RPC(3:0) = 0011
E1: Marks the time slots which are defined by
register RTR(4:1) of every received frame on
port RDO.
T1/J1: The function depend on the usage of
CAS-BR as selected by XC0.BRM.
0
1
Receive Signaling Data (RSIG)
PC(1:4).RPC(3:0) = 0100
The received CAS signaling data is sourced
by this pin. Time slots on RSIG correlate
directly to the time slot assignment on RDO.
Data Link Bit Receive (DLR)
PC(1:4).RPC(3:0) = 0101
E1: Marks the S
stream on RDO. The S
time slot 0 of every frame not containing the
frame alignment signal are selected by
register XC0.
T1/J1: Marks the DL-bit position within the
data stream on RDO.
Frame Synchronous Pulse (RFSP)
PC(1:4).RPC(3:0) = 0111
Active low framing pulse derived from the
received PCM route signal (line side, RCLK).
During loss of synchronization (bit
FRS0.LFA = 1
(not influenced during alarm simulation).
Pulse frequency: 8 kHz
Pulse width: 488 ns (E1) or 648 ns (T1/J1).
41
B
B
BRM_0, marks the time slots which are
defined by register RTR(4:1) of every
received frame on port RDO.
BRM_1, the robbed bit of each channel
in every sixth frame is marked.
B
), this pulse is suppressed
a
(8:4)-bits within the data
a
(8:4)-bit positions in
B
B
B
B
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56