pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 260

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Pulse Count Detection Register (Read/Write)
Value after reset: 00
PCD
PCD(7:0)
Pulse Count Recovery (Read/Write)
Value after reset: 00
PCR
PCR(7:0)
User’s Manual
Hardware Description
PCD7
PCR7
7
7
Pulse Count Detection
A LOS alarm is detected if the incoming data stream has no
transitions for a programmable number T consecutive pulse
positions. The number T is programmable by the PCD register and
can be calculated as follows:
T = 16 × (N+1); with 0 ≤N ≤255.
The maximum time is: 256 × 16 × 488 ns = 2 ms. Every detected
pulse resets the internal pulse counter. The counter is clocked with
the receive clock RCLK.
Pulse Count Recovery
A LOS alarm is cleared if a pulse-density is detected in the received
bit stream. The number of pulses M which must occur in the
predefined PCD time interval is programmable by the PCR register
and can be calculated as follows:
M = N+1; with 0 ≤N ≤255.
The time interval starts with the first detected pulse transition. With
every received pulse a counter is incremented and the actual counter
is compared to the contents of PCR register. If the pulse number is
higher or equal to the PCR value the LOS alarm is reset otherwise the
alarm stays active. In this case the next detected pulse transition
starts a new time interval.
H
H
260
DS1.1, 2003-10-23
PEF 2256 H/E
PCD0
PCR0
E1 Registers
0
0
FALC
(38)
(39)
®
56