pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 109

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

4.5.1.1
Depending on the selection of the synchronization signals (SYPR or RFM), different
calculation formulas are used to define the position of the synchronization pulses. These
formulas are given below, see
of SYPR and RFM is always the basic E1 bit width (488 ns), independent of the selected
system highway clock and data frequency.
SYPR Offset Calculation
T:
SD:
SC:
X:
0 ≤T ≤4:
5 ≤T ≤T
RFM Offset Calculation
MP:
SD:
SC:
X:
0
2046 ≤ MP ≤2047:
User’s Manual
Hardware Description
≤ MP ≤2045:
max
Time between beginning of SYPR pulse and beginning of next frame
(time slot 0, bit 0), measured in number of SCLKR clock intervals
maximum delay: T
Basic data rate; 2.048 Mbit/s
System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz
Programming value to be written to registers RC0 and RC1 (see
Marker position of RFM, counting in SCLKR clock cycles
(0 = bit 1, time slot 0, channel phase 0)
SC = 2.048 MHz:
SC = 4.096 MHz:
SC = 8.192 MHz:
SC = 16.384 MHz: 0 ≤MP ≤2047
Basic data rate; 2.048 Mbit/s
System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz
Programming value to be written to registers RC0 and RC1 (see
:
Receive Offset Programming
X = 4 - T
X = 2052 - T
X = MP + 2
X = MP - 2046
max
0 ≤MP ≤255
0 ≤MP ≤511
0 ≤MP ≤1023
Figure 32
= (256 × SC/SD) - 1
to
109
Figure 35
for explanation. The pulse length
Functional Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
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FALC
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