pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 130

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

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The following table shows the clock modes with the corresponding synchronization
sources.
Table 29
Mode
Master
Master
Master
Master
Slave
Slave
Slave
User’s Manual
Hardware Description
Slave mode
In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route
clock. In case of LOS the DCO-R switches automatically to master mode. If bit
CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.
Master mode
In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no
clock is supplied on pin SYNC. If an external clock on the SYNC input is applied, the
DCO-R synchronizes to this input. The external frequency can be 1.544 MHz
(LIM1.DCOC = 0; IPC.SSYF = 0), 2.048 MHz (LIM1.DCOC = 1; IPC.SSYF = 0) or
8.0 kHz (IPC.SSYF = 1; LIM1.DCOC = don’t care).
Internal
LOS Active
independent Fixed to
independent 1.544 MHz Synchronized on SYNC input (external
independent 2.048 MHz Synchronized on SYNC input (external
independent 8.0 kHz
no
no
yes
System Clocking (T1/J1)
SYNC
Input
V
Fixed to
V
1.544 or
2.048 MHz
Fixed to
V
DD
DD
DD
System Clocks
DCO-R centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
1.544 MHz, IPC.SSYF = 0, LIM1.DCOC = 0)
2.048 MHz, IPC.SSYF = 0, LIM1.DCOC = 1)
Synchronized on SYNC input (external 8.0 kHz,
IPC.SSYF = 1, CMR2.DCF = 0)
Synchronized on line RCLK
Synchronized on line RCLK
CMR1.DCS = 0:
DCO-R is centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
CMR1.DCS = 1:
Synchronized on line RCLK
130
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
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