pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 437

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Bit Error Counter (Read)
BEC(15:0)
User’s Manual
Hardware Description
Bit Error Counter
If the PRBS monitor is enabled by LCR1.EPRM = 1 this 16-bit counter
is incremented with every received PRBS bit error in the PRBS
synchronous state FRS1.LLBAD = 1. The error counter does not roll
over.
During alarm simulation, the counter is incremented continuously with
every second received bit.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the PRBS bit error counter bit
DEC.DBEC has to be set. With the rising edge of this bit updating the
buffer is stopped and the error counter is reset. Bit DEC.DBEC is
automatically reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
437
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56