pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 362

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Framer Mode Register 1 (Read/Write)
Value after reset: 00
FMR1
CTM
EDL
PMOD
CRC
User’s Manual
Hardware Description
CTM
7
Channel Translation Mode
0 =
1 =
The different channel translation modes are described in
Page
Enable DL-Bit Access through Register XDL(3:1)
Only applicable in F4, F24 or F72 frame format.
0 =
1 =
PCM Mode
For E1 application this bit must be set low. Switching from E1 to T1 or
vice versa the device needs up to 20 µs to settle up to the internal
clocking.
0 =
1 =
Enable CRC6
This bit is only significant when using the ESF format.
0 =
1 =
H
Channel translation mode 0
Channel translation mode 1
PCM 30 or E1 mode.
PCM 24 or T1/J1 mode (see RC0.SJR for T1/J1 selection).
CRC6 check/generation disabled. For transmit direction, all
CRC bit positions are set.
CRC6 check/generation enabled.
135.
Normal operation. The DL-bits are taken from system highway
or if enabled by CCR1.EDLX from the XFIFO of the signaling
controller.
DL-bit register access. The DL-bit information are taken from
the registers XDL(3:1) and overwrite the DL-bits received on
the system highway (pin XDI) or from the internal XFIFO of the
signaling controller. However, transmission of the contents of
registers XDL(3:1) is disabled if transparent mode is enabled
(FMR4.TM).
EDL
PMOD
362
CRC
ECM
SSD0
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
XAIS
0
Table 31
FALC
(1D)
®
56
on