pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 426

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

10.4
Receive FIFO - HDLC Channel 1 (Read)
Reading data from RFIFO can be done in an 8-bit (byte) or 16-bit (word) access
depending on the selected bus interface mode. The LSB is received first from the serial
interface.
The size of the accessible part of RFIFO is determined by programming the bits
CCR1.RFT(1:0) (RFIFO threshold level). It can be reduced from 32 bytes (reset value)
down to 2 bytes (four values: 32, 16, 4, 2 bytes).
Data Transfer
Up to 32 bytes/16 words of received data can be read from the RFIFO following a RPF
or a RME interrupt.
RPF Interrupt: A fixed number of bytes/words to be read (32, 16, 4, 2 bytes). The
message is not yet complete.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL, RBCH registers.
RFIFO is released by issuing the RMC (Receive Message Complete) command.
Receive Buffer Delay (Read)
RBD(5:0)
User’s Manual
Hardware Description
Detailed Description of T1/J1 Status Registers
Receive Elastic Buffer Delay
These bits informs the user about the current delay (in time slots)
through the receive elastic buffer. The delay is updated every 386 or
193 bits (SIC1.RBS(1:0)). Before reading this register the user has to
set bit DEC.DRBD in order to halt the current value of this register.
After reading RBD updating of this register is enabled. Not valid if the
receive buffer is bypassed.
000000 = Delay < 1 time slot
...
111111 = Delay > 63 time slots
426
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56