pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 394

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

RESR
TTRF
DAF
User’s Manual
Hardware Description
0
1
CMR2.IXSC = 1:
value of RESX bit has no impact on the selected edge of the PCM
highway clock but value of RESR bit is used as RESX.
Example: If RESR = 0, the rising edge of PCM highway clock is the
selected one for sampling data on XDI and vice versa.
Rising Edge Synchronous Pulse Receive
Depending on this bit all receive system interface data and marker are
clocked with the selected active edge.
0 =
1 =
Note: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is
TTR Register Function (Fractional T1/J1 Access)
Setting this bit the function of the TTR(4:1) registers are changed. A
one in each TTR register forces the XSIGM marker high for the
corresponding time slot and controls sampling of the time slots
provided on pin XSIG. XSIG is selected by PC(4:1).XPC(3:0).
Disable Automatic Freeze
0 =
1 =
latched with the first falling edge of the selected PCM highway
clock.
latched with the first rising edge of the selected PCM highway
clock.
Latched with the first falling edge of the selected PCM highway
clock.
Latched with the first rising edge of the selected PCM highway
clock.
inverse (1 = falling edge, 0 = rising edge)
occurred:
Alignment (FRS0.LFA), or receive slips (ISR3.RSP/N).
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer
is stopped if SIC2.FFS is set. Significant only if the serial
signaling access is enabled.
Signaling is automatically frozen if one of the following alarms
Automatic freezing of signaling data is disabled. Updating of the
Loss-Of-signal
394
(FRS0.LOS),
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
Loss-of-Frame-
FALC
®
56