pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 286

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

XCRC2
ITF2
XMFA2
RFT12, RFT02
User’s Manual
Hardware Description
Transmit CRC ON/OFF - HDLC Channel 2
If this bit is set, the CRC checksum will not be generated internally. It
has to be written as the last two bytes in the transmit FIFO (XFIFO2).
The transmitted frame is closed automatically with a closing flag.
Interframe Time Fill - HDLC Channel 2
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0 =
1 =
Transmit Multiframe Aligned - HDLC Channel 2
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
1 =
RFIFO2 Threshold Level - HDLC Channel 2
The size of the accessible part of RFIFO2 can be determined by
programming these bits. The number of valid bytes after an RPF
interrupt is given in the following table:
RFT12
0
0
1
1
The value of RFT(1:0)2 can be changed dynamically if reception is
not running or after the current data block has been read, but before
the command CMDR3.RMC2 is issued (interrupt controlled data
transfer).
Continuous logical "1" is output
Continuous flag sequences are output ("01111110" bit patterns)
The contents of the XFIFO2 is transmitted without multiframe
alignment.
The contents of the XFIFO2 is transmitted multiframe aligned.
RFT02
0
1
0
1
Size of Accessible Part of RFIFO2
32 bytes (default value)
16 bytes
4 bytes
2 bytes
286
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
®
56