pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 375

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Receive Control 1 (Read/Write)
Value after reset: 9C
RC1
RCO(7:0)
User’s Manual
Hardware Description
RCO7
7
Receive Offset/Receive Frame Marker Offset
Depending on the RP(A to D) pin function different offsets can be
programmed. The SYPR and the RFM pin function cannot be
selected in parallel.
Receive Offset (PC(4:1).RPC(2:0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Calculation of delay time T (SCLKR cycles) depends on the value X
of the receive offset register RC(1:0):
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0 ≤T ≤ 4:X = 4 - T
5 ≤T ≤maximum delay:X = 2052 - T
with maximum delay = (256× SC/SD) -1
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = system data rate
or
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0 ≤T ≤4:X = 4 - T + (7 × SC/SD)
5 ≤T ≤maximum delay :X = (200 × SC/SD) + 4 - T
with maximum delay = 193× SC/SD - 1
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = system data rate
Delay time T = time between beginning of time slot 0 at RDO and the
initial edge of SCLKR after SYPR goes active.
See
H
page 175
RCO5
for further description.
375
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
RCO0
0
FALC
(25)
®
56