pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 340

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

HA12, HA02
LA2
Signaling Status Register 3 (Read)
Value after reset: 00
SIS3
XDOV3
XFW3
User’s Manual
Hardware Description
XDOV3
High Byte Address Compare - HDLC Channel 2
Significant only if 2-byte address mode is selected.
In operating modes which provide high byte address recognition, the
FALC
of two individually programmable registers (RAH1, RAH2) and the
fixed values FE
Depending on the result of this comparison, the following bit
combinations are possible:
00 = RAH2 has been recognized
01 = Broadcast address has been recognized
10 = RAH1 has been recognized C/R=0 (bit 1)
11 = RAH1 has been recognized C/R=1 (bit 1)
Note: If RAH1, RAH2 contain identical values, a match is indicated by
Low Byte Address Compare - HDLC Channel 2
Significant in HDLC modes only.
The low byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared with two registers. (RAL1,
RAL2).
0 =
1 =
Transmit Data Overflow - HDLC Channel 3
More than 32 bytes have been written to the XFIFO3.
This bit is reset
Transmit FIFO Write Enable - HDLC Channel 3
Data can be written to the XFIFO3.
XFW3
•by a transmitter reset command XRES or
•when all bytes in the accessible half of the XFIFO3 have been
H
moved in the inaccessible half.
"10" or "11".
RAL2 has been recognized
RAL1 has been recognized
®
compares the high byte of a 2-byte address with the contents
XREP3
H
and FC
340
H
(broadcast address).
RLI3
CEC3
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
(9A)
®
56