pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 243

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

AXRA
ALMF
Channel Loop-Back (Read/Write)
Value after reset: 00
LOOP
ECLB
CLA(4:0)
User’s Manual
Hardware Description
7
Automatic Transmit Remote Alarm
0 =
1 =
Automatic Loss of Multiframe
0 =
1 =
Enable Channel Loop-Back
0 =
1 =
Channel Address For Loop-Back
CLA = 0 to 31 selects the channel.
During looped back the contents of the assigned outgoing channel on
ports XL1/XDOP/XOID and XL2/XDON is equal to the idle channel
code programmed at register IDLE.
H
immediately on port RDO by setting the FMR2.SAIS bit. It is
recommended to write the actual value of XC1 into this register
once again, because a write access to register XC1 sets the
read/write pointer of the transmit elastic buffer into its optimal
position to ensure a maximum wander compensation (the write
operation forces a slip).
Normal operation
The remote alarm bit is set automatically in the outgoing data
stream if the receiver is in asynchronous state (FRS0.LFA bit is
set). In synchronous state the remote alarm bit is reset.
Additionally
FMR3.EXTIW = 1 and the 400-ms time-out has elapsed, the
remote alarm bit is active in the outgoing data stream. In
cleared.
multiframe synchronous state the outgoing remote alarm bit is
Normal operation
The receiver searches a new basic- and multiframing if more
than 914 CRC errors have been detected in a time interval of
one second. The internal 914 CRC error counter is reset if the
multiframe synchronization is found. Incrementing the counter
is only enabled in the multiframe synchronous state.
Disables the channel loop-back.
Enables the channel loop-back selected by this register.
ECLB
CLA4
in
243
multiframe
CLA3
CLA2
format
CLA1
FMR2.RFS1 = 1
DS1.1, 2003-10-23
PEF 2256 H/E
CLA0
E1 Registers
0
FALC
(1F)
®
and
56