pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 436

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Errored Block Counter (Read)
EBC(15:0)
User’s Manual
Hardware Description
Errored Block Counter
In ESF format this 16-bit counter is incremented once per multiframe
if a multiframe has been received with a CRC error or an errored
frame alignment has been detected. CRC and framing errors are not
counted during asynchronous state. The error counter does not roll
over.
In F4/12/72 format an errored block contain 4/12 or 72 frames.
Incrementing is done once per multiframe if framing errors has been
detected.
During alarm simulation, the counter is incremented in ESF format
once per multiframe and in F4/12/72 format only one time.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DEBC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DEBC is automatically
reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
436
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56