pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 247

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

XCO(10:8)
Transmit Control 1 (Read/Write)
Value after reset: 9C
XC1
XCO(7:0)
User’s Manual
Hardware Description
XCO7
7
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX/XMFS is active
Refer to register XC1.
A write access to this address resets the transmit elastic buffer to its
basic starting position. Therefore, updating the value should only be
done when the FALC
centered. As a consequence a transmit slip will occur.
Transmit Offset
Calculation of delay time T (SCLKX cycles) depends on the value X
of the “Transmit Offset” register XC(1:0):
0 ≤T ≤4: X = 4 - T
5 ≤T ≤maximum delay: X = 256 × SC/SD - T + 4)
with maximum delay = (256 × SC/SD) -1
with SC = system clock defined by SIC1.SSC(1:0)
with SD = 2.048 MHz
Delay time T = time between beginning of time slot 0 (bit 0, channel
phase 0) at XDI/XSIG and the initial edge of SCLKX after
SYPX/XMFS goes active.
See
H
page 114
direction together with these bits the TSWM.TSA(8:4) bits must
be set to enable transmission to the remote end transparently
through the FALC
for further description.
®
56 is initialized or when the buffer should be
247
®
56.
DS1.1, 2003-10-23
PEF 2256 H/E
XCO0
E1 Registers
0
FALC
(23)
®
56