mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 489
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mc68hc916y3
Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC916Y3.pdf
(500 pages)
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IMM8 4-9
Immediate addressing modes 4-9
Impedance 10-22
In-circuit debugger (ICD16/ICD32) C-1
INCP D-76
Increment prescaler (INCP) D-76
Indexed addressing modes 4-10
Inductors 10-14
Inherent addressing modes 4-10
Input
Instruction
Interchannel communication 14-4
Intermodule bus (IMB) 3-3, 13-1
Internal
Interrupt
MC68HC16Y3/916Y3
USER’S MANUAL
capture
capture/input transition counter (ITC) 14-7
leakage errors 10-24
execution model 4-35
fetches 4-7
pipeline 4-35
set for CPU16 4-11
timing 4-36
bus
register map 3-18
VCO frequency 5-9
acknowledge
arbitration 5-3, 11-3, 13-6
exception processing 5-56
level (IL)
priority
(IC) pins 13-7
/output compare (IC4/OC5) pin 13-7
4/output compare 5 13-15
conditioning signals 13-13
edge control bit field (EDGE) D-80
flags (ICF) D-82
functions 13-11
interrupt
timing example 13-14
error (BERR) 5-16, 5-17
monitor 5-16
and arbitration 5-57
bus cycles 5-59
IARB field
for QSPI (ILQSPI) D-48
for SCI (ILSCI) D-48
adjust (IPA) D-76
and recognition 5-56
level field (IPL) 5-66, D-23
(I4/O5) bit D-79
flag (I4/O5F) D-82
interrupt enable bit (I4/O5) D-81
enable (ICI) bit D-81
logic 13-13
GPT D-76
MCCI D-63
QSM D-47
SCIM2 5-57, D-7
TPU 14-6, D-89
Freescale Semiconductor, Inc.
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Interrupts
Inter-transfer delay 11-6
INTV D-48, D-64
IOUT 10-19
IP 4-4, 11-3, 14-6, D-3
IPA D-76
IPIPE0 4-43
IPIPE1 4-43
IPL D-23
IRQ 5-56, 14-5
ISB 6-2
ITC 14-7
IX 4-3
IY 4-3
IZ 4-3
Junction leakage 10-24
Leakage error 10-24
Length of delay after transfer (DTL) D-57
Level-sensitivity 5-56
LJSRR D-44
LJURR D-45
LOC D-9
LOCK 7-3, D-28
Lock registers (LOCK) D-28
Logic
Loop mode (LOOPS) D-50, D-69
LOOPQ D-58
LOOPS D-50, D-69
Loss of clock reset (LOC) D-9
Low power stop (LPSTOP)
Low-power
processing summary 5-58
vector D-64
GPT 13-5
QSM 11-3
SCIM2 5-55
TPU 14-5
analyzer pod connectors C-2
levels (definition) 2-9
MRM 7-3
SRAM 6-2
TPU 14-16
broadcast cycle 5-34
CPU space cycle 5-34
interrupt mask level 5-34
stop mode enable (STOP)
mask (IP) field 4-4, 5-56, 11-3, 13-6, 14-6, D-3
number 11-3, 13-6
ADC 10-4, D-38
GPT 13-3, D-76
MCCI 12-2, D-63
MRM D-27
field (INTV) D-48
–L–
–J–
MOTOROLA
I-7
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