mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 458

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

TMSK1/TMSK2 — Timer Interrupt Mask Registers 1–2
D.9.10 Input Capture 4/Output Compare 5 Register
TI4/O5 — Input Capture 4/Output Compare 5 Register
D.9.11 Timer Control Registers 1 and 2
TCTL1/TCTL2 — Timer Control Registers 1–2
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
EDGE[4:1] — Input Capture Edge Control
D.9.12 Timer Interrupt Mask Registers 1 and 2
D-80
MOTOROLA
I4/O5I
OM5
15
15
0
0
RESET:
RESET:
This register serves either as input capture register 4 or output compare register 5, de-
pending on the state of I4/O5 in PACTL. It is reset to $FFFF.
TCTL1 determines output compare mode and output logic level. TCTL2 determines
the type of input capture to be performed.
Each pair of bits specifies an action to be taken when output comparison is successful.
Refer to Table D-49.
Each pair of bits configures input sensing logic for the corresponding input capture.
Refer to Table D-50.
OL5
14
14
0
0
OM4
13
13
0
0
OCI[4:1]
OL4
12
12
0
0
OM/OL[5:2]
EDGE[4:1]
00
01
10
11
00
01
10
11
Freescale Semiconductor, Inc.
OM3
11
11
0
0
For More Information On This Product,
Table D-49 OM/OL[5:2] Effects
Table D-50 EDGE[4:1] Effects
OL3
10
10
0
0
Go to: www.freescale.com
ICI[3:1]
OM2
9
0
9
0
Capture on any (rising or falling) edge
Timer disconnected from output logic
OL2
Capture on falling edge only
Capture on rising edge only
8
0
8
0
Clear OCx output line to 0
Set OCx output line to 1
Toggle OCx output line
Capture disabled
EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A
Configuration
Action Taken
TOI
7
0
7
0
6
0
0
6
0
PAOVI
5
0
5
0
PAII
4
0
4
0
CPROUT
3
0
3
0
MC68HC16Y3/916Y3
USER’S MANUAL
2
0
2
0
$YFF91C
$YFF91E
$YFF920
CPR[2:0]
1
0
1
0
0
0
0
0