mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 436

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
SPCR3 — QSPI Control Register
SPSR — QSPI Status Register
WREN — Wrap Enable
WRTO — Wrap To
Bit 12 — Not Implemented
ENDQP[3:0] — Ending Queue Pointer
Bits [7:4] — Not Implemented
NEWQP[3:0] — New Queue Pointer Value
D.7.13 QSPI Control Register 3
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
HMIE — HALTA and MODF Interrupt Enable
HALT — Halt QSPI
D-58
MOTOROLA
15
RESET:
This field contains the last QSPI queue address.
This field contains the first QSPI queue address.
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and
the halt control bit. SPCR3 must be initialized before QSPI operation begins. Writing
a new value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains
information concerning the current serial transmission.
LOOPQ controls feedback on the data serializer for testing.
HMIE enables interrupt requests generated by the HALTA status flag or the MODF
status flag in SPSR.
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
0 = Wrap to pointer address $0.
1 = Wrap to address in NEWQP.
0 = Feedback path disabled.
1 = Feedback path enabled.
0 = HALTA and MODF interrupts disabled.
1 = HALTA and MODF interrupts enabled.
0 = QSPI operates normally.
1 = QSPI is halted for subsequent restart.
14
NOT USED
13
12
Freescale Semiconductor, Inc.
11
For More Information On This Product,
LOOPQ
10
0
Go to: www.freescale.com
HMIE
9
0
HALT
8
0
SPIF
7
0
MODF
6
0
HALTA
5
0
USED
NOT
4
3
0
MC68HC16Y3/916Y3
USER’S MANUAL
CPTQP[3:0]
2
0
$YFFC1E
$YFFC1F
1
0
0
0

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