mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 234

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

11.2 QSM Registers and Address Map
11.2.1 QSM Global Registers
11.2.1.1 Low-Power Stop Mode Operation
11-2
MOTOROLA
The QSPI provides peripheral expansion or interprocessor communication through a
full-duplex, synchronous, three-line bus. Four programmable peripheral chip-selects
can select up to sixteen peripheral devices by using an external 1 of 16 line selector.
A self-contained RAM queue allows up to sixteen serial transfers of eight to sixteen
bits each or continuous transmission of up to a 256-bit data stream without CPU16 in-
tervention. A special wrap-around mode supports continuous transmission/reception
of data.
The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates
in either full- or half-duplex mode. There are separate transmitter and receiver enable
bits and dual data buffers. A modulus-type baud rate generator provides rates from 64
to 524 kbaud with a 16.78 MHz system clock. Word length of either eight or nine bits
is software selectable. Optional parity generation and detection provide either even or
odd parity check capability. Advanced error detection circuitry catches glitches of up
to 1/16 of a bit time in duration. Wake-up functions allow the CPU16 to run uninterrupt-
ed until meaningful data is available.
There are four types of QSM registers: QSM global registers, QSM pin control regis-
ters, QSPI registers, and SCI registers. Refer to 11.2.1 QSM Global Registers and
11.2.2 QSM Pin Control Registers for a discussion of global and pin control registers.
Refer to 11.3.1 QSPI Registers and 11.4.1 SCI Registers for further information about
QSPI and SCI registers. Writes to unimplemented register bits have no effect, and
reads of unimplemented bits always return zero. Refer to 5.2.1 Module Mapping for
more information about how the state of MM affects the system.
The QSM configuration register (QSMCR) controls the interface between the QSM
and the intermodule bus. The QSM test register (QTEST) is used during factory test
of the QSM. The QSM interrupt level register (QILR) determines the priority of inter-
rupts requested by the QSM and the vector used when an interrupt is acknowledged.
The QSM interrupt vector register (QIVR) contains the interrupt vector for both QSM
submodules. QILR and QIVR are 8-bit registers located at the same word address.
When the STOP bit in QSMCR is set, the system clock input to the QSM is disabled
and the module enters low-power stop mode. QSMCR is the only register guaranteed
to be readable while STOP is asserted. The QSPI RAM is not readable in low-power
stop mode. However, writes to RAM or any register are guaranteed valid while STOP
is asserted. STOP can be set by the CPU16 and by reset.
Freescale Semiconductor, Inc.
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