mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 217

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC16Y3/916Y3
USER’S MANUAL
Mode 2 — A single conversion is performed on each of four sequential input channels,
starting with the channel specified by the value in CD:CA. Each result is stored in a
separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADSTAT is set
as each register is filled. The SCF bit in ADSTAT is set when the last conversion is
complete.
Mode 3 — A single conversion is performed on each of eight sequential input chan-
nels, starting with the channel specified by the value in CD:CA. Each result is stored
in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in ADSTAT
is set as each register is filled. The SCF bit in ADSTAT is set when the last conversion
is complete.
Mode 4 — Continuous four-conversion sequences are performed on a single input
channel specified by the value in CD:CA. Each result is stored in a separate result reg-
ister (RSLT0 to RSLT3). Previous results are overwritten when a sequence repeats.
The appropriate CCF bit in ADSTAT is set as each register is filled. The SCF bit in AD-
STAT is set when the first four-conversion sequence is complete.
Mode 5 — Continuous eight-conversion sequences are performed on a single input
channel specified by the value in CD:CA. Each result is stored in a separate result reg-
ister (RSLT0 to RSLT7). Previous results are overwritten when a sequence repeats.
The appropriate CCF bit in ADSTAT is set as each register is filled. The SCF bit in AD-
STAT is set when the first eight-conversion sequence is complete.
Mode 6 — Continuous conversions are performed on each of four sequential input
channels, starting with the channel specified by the value in CD:CA. Each result is
stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in AD-
STAT is set as each register is filled. The SCF bit in ADSTAT is set when the first four-
conversion sequence is complete.
Mode 7 — Continuous conversions are performed on each of eight sequential input
channels, starting with the channel specified by the value in CD:CA. Each result is
stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in AD-
STAT is set as each register is filled. The SCF bit in ADSTAT is set when the first eight-
conversion sequence is complete.
Table 10-7 is a summary of ADC operation when MULT is cleared (single channel
modes). Table 10-8 is a summary of ADC operation when MULT is set (multi-channel
modes). Number of conversions per channel is determined by SCAN. Channel num-
bers are given in order of conversion.
Freescale Semiconductor, Inc.
For More Information On This Product,
ANALOG-TO-DIGITAL CONVERTER
Go to: www.freescale.com
MOTOROLA
10-9