mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 111

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.2.1 Module Mapping
5.2.2 Interrupt Arbitration
5.2.3 Single-Chip Operation Support
MC68HC16Y3/916Y3
USER’S MANUAL
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping (MM) bit in SCIMCR determines where the
control register block is located in the system memory map. When MM = 0, register
addresses range from $7FF000 to $7FFFFF; when MM = 1, register addresses range
from $FFF000 to $FFFFFF.
In MC68HC16Y3/916Y3 MCUs, ADDR[23:20] follow the logic state of ADDR19 unless
externally driven. MM corresponds to IMB ADDR23. If MM is cleared, the SCIM2 maps
IMB modules into address space $7FF000 – $7FFFFF, which is inaccessible to the
CPU16. Modules remain inaccessible until reset occurs. The reset state of MM is one,
but the bit can be written once. Initialization software should make certain MM remains
set.
Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbi-
tration between interrupt requests of the same priority is performed by serial conten-
tion between IARB field bit values. Contention will take place whenever an interrupt
request is acknowledged, even when there is only a single request pending. For an
interrupt to be serviced, the appropriate IARB field must have a non-zero value. If an
interrupt request from a module with an IARB field value of %0000 is recognized, the
CPU16 processes a spurious interrupt exception.
Because the SCIM2 routes external interrupt requests to the CPU16, the SCIM2 IARB
field value is used for arbitration between internal and external interrupts of the same
priority. The reset value of IARB for the SCIM2 is %1111, and the reset IARB value for
all other modules is %0000, which prevents SCIM2 interrupts from being discarded
during initialization. Refer to 5.8 Interrupts for a discussion of interrupt arbitration.
The SCIMCR contains three bits that support single-chip operation. Setting the CPU
development support disable bit (CPUD) disables (places in a high impedance state)
the instruction tracking pins whenever the FREEZE signal is not asserted. The instruc-
tion tracking pins on CPU16-based MCUs are IPIPE1 and IPIPE0. When CPUD is
cleared to zero, the instruction tracking pins operate normally.
Setting the address bus disable bit (ABD) disables ADDR[2:0] by placing the pins in a
high-impedance state. During single-chip operation, the ADDR[23:3] pins are config-
ured for discrete output or input/output, and ADDR[2:0] should normally be disabled.
Setting the R/W disable bit (RWD) disables the R/W pin. This pin is not normally used
during single-chip operation.
The reset state of each of these three bits is one if BERR is held low during reset (con-
figuring the MCU for single-chip operation) or zero if BERR is held high during reset.
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MOTOROLA
5-3