mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 304

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
13-16
MOTOROLA
PCLK
In event counting mode, the counter increments each time a selected transition of the
pulse accumulator input(PAI) pin is detected. The maximum clocking rate is the sys-
tem clock divided by four.
In gated time accumulation mode a clock increments PACNT while the PAI pin is in
the active state. There are four possible clock sources.
Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator
flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse
accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has
rolled over from $FF to $00. This can be used to extend the range of the counter be-
yond eight bits.
PAI
CAPTURE/COMPARE CLK
PRESCALER 512
TCNT OVERFLOW
SYNCHRONIZER
DIGITAL FILTER
Figure 13-5 Pulse Accumulator Block Diagram
PACTL
TMSK2
&
Freescale Semiconductor, Inc.
For More Information On This Product,
MUX
DETECT
LOGIC
GENERAL-PURPOSE TIMER
EDGE
Go to: www.freescale.com
MUX
2:1
INTERNAL
DATA BUS
OVERFLOW
ENABLE
TFLG2
8-BIT COUNTER
PACNT
MC68HC16Y3/916Y3
USER’S MANUAL
INTERRUPT
REQUESTS
10
11
16/32 PULSE ACC BLOCK

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