mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 290

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

13.2 GPT Registers and Address Map
13-2
MOTOROLA
The GPT programming model consists of a configuration register (GPTMCR), parallel
I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2,
TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL),
pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,
PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1,
TMSK2). Functions of the module configuration register are discussed in 13.3 Special
Modes of Operation and <Bold>11.4 Polled and Interrupt-Driven Operation. Other reg-
ister functions are discussed in the appropriate sections.
All registers can be accessed using byte or word operations. Certain capture/compare
registers and pulse-width modulation registers must be accessed by word operations
to ensure coherency. If byte accesses are used to read a register such as the timer
counter register (TCNT), there is a possibility that data in the byte not being accessed
will change while the other byte is read. Both bytes must be accessed at the same
time.
The modmap (MM) bit in the single-chip integration module configuration register
(SCIMCR) defines the most significant bit (ADDR23) of the IMB address for each reg-
ister in the MCU. Because the CPU16 drives ADDR[23:20] to the same logic state as
ADDR[19:0], MM must equal one.
IC1/PGP0
IC3/PGP2
IC2/PGP1
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 13-1 GPT Block Diagram
GENERAL-PURPOSE TIMER
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CAPTURE/COMPARE UNIT
PULSE ACCUMULATOR
BUS INTERFACE
PRESCALER
PWM UNIT
IMB
OC1/PGP3
OC2/OC1/PGP4
OC3/OC1/PGP5
OC4/OC1/PGP6
IC4/OC5/OC1/PGP7
PAI
PWMA
PWMB
PCLK
MC68HC16Y3/916Y3
USER’S MANUAL
GPT BLOCK