mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 434

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

D.7.11 QSPI Control Register 1
SPCR1 — QSPI Control Register 1
SPE — QSPI Enable
DSCKL[6:0] — Delay before SCK
D-56
MOTOROLA
RESET:
SPE
15
0
Giving SPBR[7:0] a value of zero or one disables the baud rate generator. SCK is
disabled and assumes its inactive state value. No serial transfers occur. At reset, the
SCK baud rate is initialized to one-eighth of the system clock frequency.SPBR has 254
active values. Table D-39 lists several possible baud values and the corresponding
SCK frequency based on a 16.78 MHz system clock.
SPCR1 enables the QSPI and specifies transfer delays. SPCR1 must be written last
during initialization because it contains SPE. Writing a new value to SPCR1 while the
QSPI is enabled disrupts operation.
When the DSCK bit is set in a command RAM byte, this field determines the length of
the delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip-
select pins. The following equation determines the actual delay before SCK:
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
14
0
13
0
16.78 MHz
12
0
Table D-39 Examples of SCK Frequencies
f
DSCKL[6:0]
sys
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
SPBR[7:0]
SCK Baud Rate
10
1
Division Ratio
Go to: www.freescale.com
Required
168
510
9
0
16
34
4
8
=
------------------------------------------------------------------------- -
2 SCK Baud Rate Desired
8
0
Value of SPBR
or
7
0
=
255
17
84
------------------------------------ -
2 SPBR[7:0]
2
4
8
6
0
f
sys
f
sys
5
0
Actual SCK
Frequency
4.19 MHz
2.10 MHz
1.05 MHz
493 kHz
100 kHz
33 kHz
4
0
DTL[7:0]
3
0
MC68HC16Y3/916Y3
USER’S MANUAL
2
1
$YFFC1A
1
0
0
0