mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 450

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
D.8.13 SPI Control Register
SPCR — SPI Control Register
SPIE — SPI Interrupt Enable
SPE — SPI Enable
WOMP — Wired-OR Mode for SPI Pins
MSTR — Master/Slave Mode Select
CPOL — Clock Polarity
CPHA — Clock Phase
LSBF — Least Significant Bit First
D-72
MOTOROLA
RESET:
SPIE
15
0
The SPCR contains parameters for configuring the SPI. The register can be read or
written at any time.
CPOL is used to determine the inactive state of the serial clock (SCK). It is used with
CPHA to produce a desired clock/data relationship between master and slave devices.
CPHA determines which edge of SCK causes data to change and which edge causes
data to be captured. CPHA is used with CPOL to produce a desired clock/data rela-
tionship between master and slave devices.
0 = SPI interrupts disabled.
1 = SPI interrupts enabled.
0 = SPI is disabled.
1 = SPI is enabled.
0 = Outputs have normal CMOS drivers.
1 = Pins designated for output by MDDR have open-drain drivers, regardless of
0 = SPI is a slave device.
1 = SPI is system master.
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
0 = Data captured on the leading edge of SCK and changed on the trailing edge of
1 = Data is changed on the leading edge of SCK and captured on the trailing edge
0 = Serial data transfer starts with LSB.
1 = Serial data transfer starts with MSB.
SPE
14
0
whether the pins are used as SPI outputs or for general-purpose I/O, and
regardless of whether the SPI is enabled.
SCK.
of SCK.
WOMP
13
0
MSTR
12
0
Freescale Semiconductor, Inc.
CPOL
11
For More Information On This Product,
0
CPHA
10
0
Go to: www.freescale.com
LSBF
9
0
SIZE
8
1
7
0
6
0
5
0
4
0
SPBR[7:0]
3
0
MC68HC16Y3/916Y3
USER’S MANUAL
2
1
$YFFC38
1
0
0
0

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