mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 106

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.14.5.4 Returning from BDM
4.14.5.5 BDM Serial Interface
4-44
MOTOROLA
BDM is terminated when a resume execution (GO) command is received. GO refills
the instruction pipeline from address (PK : PC - $0006). FREEZE is negated before
the first prefetch. Upon negation of FREEZE, the BDM serial subsystem is disabled
and the DSO/DSI signals revert to IPIPE0/IPIPE1 functionality.
The BDM serial interface uses a synchronous protocol similar to that of the Motorola
serial peripheral interface (SPI). Figure 4-7 is a diagram of the serial logic required to
use BDM with a development system.
The development system serves as the master of the serial link, and is responsible for
the generation of the serial interface clock signal (DSCLK).
Serial clock frequency range is from DC to one-half the CPU16 clock frequency. If
DSCLK is derived from the CPU16 system clock, development system serial logic can
be synchronized with the target processor.
The serial interface operates in full-duplex mode. Data transfers occur on the falling
edge of DSCLK and are stable by the following rising edge of DSCLK. Data is trans-
mitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide, which includes 16 data bits and a status/control
bit. Bit 16 indicates status of CPU-generated messages.
Command and data transfers initiated by the development system must clear bit 16.
All commands that return a result return 16 bits of data plus one status bit.
Freescale Semiconductor, Inc.
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MC68HC16Y3/916Y3
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