cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 99

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.10.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers
The bit rate divisor and line control register is a 19-bit read / write register. Writing to these registers sets the bit rate
and mode of operation for the internal UARTs.
DS502PP2
0:11
12
13
14
15
16
31:19
Bit
(address 0x8000.04C0 and 0x8000.14C0)
WRDLEN
Bit rate divisor: This 12-bit field sets the bit rate. If the system is operating from the PLL clock,
then the bit rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided
internally by 16 to give the bit rate. The formula to give the divisor value for any bit rate when
operating from the PLL clock is: Divisor = 230400 / (bit rate divisor + 1). A value of zero in this
field is illegal when running from the PLL clock. The tables below show some example bit rates
with the corresponding divisor value.The table below shows the bit rates available for 18.432 MHz
operation.
BREAK: Setting this bit will drive the TX output active (high) to generate a break.
PRTEN: Parity enable bit. Setting this bit enables parity detection and generation
EVENPRT: Even parity bit. Setting this bit sets parity generation and checking to even parity,
clearing it sets odd parity. This bit has no effect if the PRTEN bit is clear.
XSTOP: Extra stop bit. Setting this bit will cause the UART to transmit two stop bits after each
data byte, while clearing it will transmit one stop bit after each data byte.
FIFOEN: Set to enable FIFO buffering of RX and TX data. Clear to disable the FIFO (i.e., set its
depth to one byte).
18:17
Divisor Value
2094
191
15
23
95
11
0
1
2
3
5
FIFOEN
16
From the PLL Clock
Bit Rate Running
115200
76800
57600
38400
19200
14400
9600
2400
1200
110
—
XSTOP
15
Description
EVENPRT
14
PRTEN
13
BREAK
12
CS89712
Bit rate divisor
11:0
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