cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 17

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

2.7.2
The clock frequency used for the CPU and the bus-
es is controlled by programming the CLKCTL[1:0]
bits in the SYSCON3 register. When this register is
written, clock switching logic waits until the clock
that is currently in use and the newly programmed
clock source are both low, and then switches from
the previous clock frequency to the new clock with-
out a glitch on the clocks.
2.7.3
A 20 MHz quartz crystal or CMOS clock input is
required by the Ethernet port. If a CMOS clock in-
put is used, it should be connected the to XTAL1
pin, with the XTAL2 pin left open. The clock sig-
nal should be 20 MHz 0.01% with a duty cycle
between 40% and 60%. The specifications for the
crystal are described in Section 5.3.
2.8 Interrupt Controller
When unexpected events arise during the execution
of a program (i.e., interrupt or memory fault) an ex-
ception is usually generated. When these excep-
tions occur at the same time, a fixed priority system
determines the order in which they are handled.
Table 6
DS502PP2
Interrupt /
Note: t42=0.125 sec. to 0.25 sec.
(internal)
WAKEUP
EXPCLK
CLKEN
RUN
shows the priority order of the exceptions.
Dynamic Clock Switching
Ethernet Port Clock Oscillator
Figure 4. CLKEN Timing Exiting the Standby State
t42
The CS89712 interrupt controller has two interrupt
types: interrupt request (IRQ) and fast interrupt re-
quest (FIQ). The interrupt controller has the ability
to control interrupts from 22 different FIQ and IRQ
sources. Of these, seventeen are mapped to the IRQ
input and five sources are mapped to the FIQ input.
FIQs have a higher priority than IRQs. If two inter-
rupts are received from within the same group (IRQ
or FIQ), the order in which they are serviced must
be resolved in software. All interrupts are level sen-
sitive; that is, they must conform to the following
sequence:
1) The interrupting device (either external or in-
2) If the appropriate bit is set in the interrupt mask
ternal) asserts the appropriate interrupt.
register, then either a FIQ or an IRQ will be as-
Priority
Highest
Lowest
.
.
.
.
Table 6. Exception Priority Handling
Undefined Instruction,
Software Interrupt
Prefetch Abort
Exception
Data Abort
Reset
IRQ
FIQ
CS89712
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