cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 122

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.18.7 Transmit Command Status register (TxCMD, address offset 108h)
This register contains the latest transmit command which describes how the next packet should be sent. The com-
mand must be written to Ethernet Port offset 0144h in order to initiate a transmission. The software can read the
command from this register (offset 0108h). See Section 2.34, “Transmit Operation” .
After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM
is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE-
PROM” .
Regster value is: 0000 0000 0000 1001
Note: The CS89712 does not transmit a frame if TxLength < 3
122
5:0
7:6
8
9
C
D
InhibitCRC
Bit
TxStart
7:6
C
001001: These bits provide an internal address used by the CS89712 to identify this as register
9, the Transmit Command Register. When reading this register, these bits will be 001001, where
the LSB corresponds to Bit 0.
TxStart: This pair of bits determines how many bytes are transferred to the CS89712 before the
MAC starts the packet transmit process.
Force: When set in conjunction with a new transmit command, any transmit frames waiting in
the transmit buffer are deleted. If a previous packet has started transmission, that packet is ter-
minated within 64 bit times with a bad CRC.
Onecoll: When this bit is set, any transmission will be terminated after only one collision. When
clear, the CS89712 allows up to 16 normal collisions before terminating the transmission.
InhibitCRC: When set, the CRC is not appended to the transmission.
TxPadDis: When TxPadDis is clear, if the software gives a transmit length less than 60 bytes
and InhibitCRC is set, then the CS89712 pads to 60 bytes. If the software gives a transmit length
less than 60 bytes and InhibitCRC is clear, then the CS89712 pads to 60 bytes and appends the
CRC.
When TxPadDis is set, the CS89712 allows the transmission of runt frames (a frame less than
64 bytes). If InhibitCRC is clear, the CS89712 appends the CRC. If InhibitCRC is set, the
CS89712 does not append the CRC
Bit 7
0
0
1
1
001001
5:0
B
1
Bit 6
0
1
0
Table 72. Transmit Command Status
Start transmission after the entire frame is in the CS89712
Start transmission after 5 bytes are in the CS89712
Start transmission after 381 bytes are in the CS89712
Start transmission after 1021 bytes are in the CS89712
A
F
Description
Onecoll
E
9
TxPadDis
CS89712
Force
D
8
DS502PP2