cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 63

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

located at Ethernet Port offset address 0150h. If the
decoder output and the Logical Address Filter bit
match, the frame passes the hash filter and the
Hashed bit (RxEvent register bit 9) is set. If the two
do not match, the frame fails the filter and the
Hashed bit is clear.
Whenever the hash filter is passed by a "good"
frame, the RxOK bit (RxEvent register bit 8) is set
and the bits in the HR are mapped to the Hash Table
Index bits (RxEvent register, bits A through F).
2.33.6
Table 28
Event register for each output of the hash and ad-
dress filters, and describes an exception to normal
processing. That exception can occur when the
hash-filter Broadcast address matches a bit in the
Logical Address Filter. To properly account for this
exception, the software driver should use the fol-
lowing test to determine if the RxEvent register
contains a normal RxEvent (meaning bits E-A are
used for Extra data, Runt, CRC Error, Broadcast
and IndividualAdr) or a hash-table RxEvent (mean-
ing bits F-A contain the Hash Table Index).
If bit Hashed =0, or bit RxOK=0, or (bits F-A = 02h
and the destination address is all ones) then Rx-
Event contains a normal RxEvent, else RxEvent
contained a hash RxEvent.
DS502PP2
Broadcast Frame Hashing Exception
describes in detail the content of the Rx-
Hashed
bit
to
OR gate
64-input
Destination Address (DA)
from incoming frame
1
Figure 21. Hash Filter Operation
Written into PacketPage base + 150h
64-bit Logical Address Filter (LAF)
Logic
CRC
2.34 Transmit Operation
2.34.1 Overview
Packet transmission occurs in two phases. In the
first phase, the Ethernet frame is moved into the
Ethernet port’s buffer memory. This phase begins
with the software issuing a Transmit Command.
This informs the CS89712 that a frame is to be
transmitted and tells the chip when (i.e. after 5,
381, or 1021 bytes have been transferred or after
the full frame has been transferred to the CS89712)
and how the frame should be sent (i.e. with or with-
out CRC, with or without pad bits, etc.). The soft-
ware follows the Transmit Command with the
Transmit Length, indicating how much buffer
space is required. When buffer space is available,
the software writes the Ethernet frame into the
Ethernet port’s internal memory.
In the second phase of transmission, the Ethernet
port converts the frame into an Ethernet packet then
transmits it onto the network. The second phase be-
gins with the Ethernet port transmitting the pream-
ble and Start-of-Frame delimiter as soon as the
proper number of bytes has been transferred into its
transmit buffer (5, 381, 1021 bytes or full frame,
depending on configuration). The preamble and
Start-of-Frame delimiter are followed by the data
transferred into the on-chip buffer by the software
6-to-64 decoder
(MSB)
6-bit Hash Register (HR)
32-bit CRC value
[Hash Table Index]
(LSB)
64
CS89712
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