cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 11
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cs89712
Manufacturer Part Number
cs89712
Description
High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS89712.pdf
(170 pages)
- Current page: 11 of 170
- Download datasheet (2Mb)
nPOR is the highest priority reset signal. When ac-
tive (low), it will reset all storage elements in the
CS89712. nPOR active forces nSYSRES and nST-
BY active. nPOR will only be active after the
CS89712 is first powered up and not during any
other resets. nPOR active clears all flags in the sta-
tus register except for the cold reset flag (CLD-
FLG) bit (SYSFLG, bit 15), which is set.
nSYSRES is generated internally in the CS89712 if
either nPOR, nPWRFL, or nURESET are active. It
is the second highest priority reset signal, used to
asynchronously reset most internal registers.
nSYSRES activation forces nSTBY and RUN low,
and resets the CS89712 leaving it in the Standby
State.
The nSTBY and RUN signals are high when the
CS89712 is in the Operating or Idle States and low
when in the Standby State. The main system clock
is valid when nSTBY is high. The nSTBY signal
will disable any peripheral block that is clocked
from the master clock source (i.e., everything ex-
cept for the RTC). However, when in Snooze State,
the LCD controller and the DC to DC converter in-
terface peripherals will NOT be disabled.
In general, a system reset will clear all registers and
nSTBY will disable all peripherals that require a
main clock, with the exception of the Snooze State
operation as described above. The following pe-
ripherals are always disabled by a low level on
nSTBY: two UARTs and IrDA SIR encoder, timer
counters, telephony codec, and the two SSI inter-
faces. In addition, when in the Standby State, the
LCD controller and PWM drive are also disabled.
2.5 Ethernet Port Reset and Initialization
Different considerations apply to resetting and ini-
tializing the Ethernet Port.
2.5.1
Three different conditions cause the Ethernet port
to reset its Ethernet internal registers and circuits.
DS502PP2
Reset
2.5.1.1
When power is applied, the Ethernet port maintains
reset until the voltage at the supply pins reaches ap-
proximately 2.5 V. The Ethernet port comes out of
reset once Vcc is greater than approximately 2.5 V
and the crystal oscillator has stabilized.
2.5.1.2
There is a chip-wide reset whenever the RESET bit
(SelfCTL Register, Bit 6) is set.
2.5.1.3
Whenever the Ethernet port enters Software Sus-
pend mode, all registers and circuits are reset.
Upon exit, there is a chip-wide reset.
2.5.2
After a reset, the Ethernet port goes through a self
configuration. This includes calibrating on-chip
analog circuitry, and reading EEPROM for validity
and configuration. Time required for the reset cali-
bration is typically 10 ms. Software drivers should
not access registers internal to the CS89712 Ether-
net during this time. When calibration is done, bit
INITD in the Self Status Register is set indicating
that initialization is complete, and the SIBUSY bit
in the same register is cleared indicating the EE-
PROM is no longer being read.
2.5.3
After each reset (except EEPROM Reset), the
CS89712’s Ethernet port checks the sense of the
EEDataIn pin to see if an external EEPROM is
present. EEDI high indicates presence of an EE-
PROM and the Ethernet port automatically loads
the configuration data stored in the EEPROM into
its internal registers (see next section). If EEDI is
low, an EEPROM is not present and the Ethernet
port resets with the register values in
An optional low-cost serial EEPROM can be used
to store configuration information that is automati-
Allowing Time for Reset Operation
Initialization
Power-Up Reset
Software Initiated Reset
Software Suspend
CS89712
Table
2.
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