cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 64

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

(Destination Address, Source Address, Length
field and LLC data). If the frame is less than 64
bytes, including CRC, the CS89712 adds pad bits if
configured to do so. Finally, the CS89712 appends
the proper 32-bit CRC value.
2.34.2 Transmit Configuration
After each reset, the Ethernet port must be config-
ured for transmit operation. This can be done auto-
matically using an attached EEPROM, or by
writing configuration commands to the Ethernet
port’s internal registers (see Section 2.6, “Ethernet
EEPROM Configurations”). The items that must
be configured include which physical interface to
use and which transmit events cause interrupts.
2.34.2.1 Configuring the Physical Interface
Configuring the Physical Interface is accomplished
via the LineCTL register. Bit 6 enables reception
and bit 9 enables transmission, while bits B and D
control backoff and deferral. See Section 3.18.12
on page 127 for LineCTL details.
Note that the CS89712 transmits in 10BASE-T
mode when no link pulses are being received only
if bit DisableLT is set in the Test Control register.
2.34.2.2 Selecting Interrupt Events
The TxCFG and BufCFG registers are used to de-
termine which transmit events will cause inter-
rupts. TxCFG [B:8] and F, and BufCFG [9:8] and
C are used. Refer to Section 3.18.5 and
Section 3.18.8 for details.
2.34.3
When software configures these registers it does
not need to change them for subsequent packet
transmissions. The TxCFG or BufCFG register bits
may be changed at any time. The effects of the
change are noticed immediately. Any changes in
the Interrupt Enable (iE) bits may affect the packet
currently being transmitted.
64
Changing the Configuration
If the LineCTL register bits are changed after ini-
tialization, the ModBackoffE bit and any receive
related bit (LoRxSquelch, SerRxON) may be
changed at any time.
2.34.4 Enabling CRC Generation/Padding
Whenever the software issues a Transmit Request
command, it must indicate whether or not the Cy-
clic Redundancy Check (CRC) value should be ap-
pended to the transmit frame, and whether or not
pad bits should be added (if needed). Bits C and D
of TxCMD are used, refer to
page
2.34.5 Individual Packet Transmission
Whenever the software has a packet to transmit, it
must issue a Transmit Request to the Ethernet port
consisting of the following three operations in the
exact order shown:
1) The software must write a Transmit Command
2) The software must write the frame’s length to
3) Software must read the BusST register.
The information written to the TxCMD register
tells the Ethernet port how to transmit the next
frame. Appropriate bits in TxCMD are 6:9, C and
D. Refer to
For each individual packet transmission, software
must issue a complete Transmit Request. Further-
more, the software must write to the TxCMD reg-
ister before each packet transmission, even if the
contents of the TxCMD register do not change.
2.34.6 Transmit in Poll Mode
In poll mode, Rdy4TxiE bit (BufCFG register bit 8)
must be clear (Interrupt Disabled). The transmit op-
eration occurs in the following order:
to the TxCMD register. The contents of the Tx-
CMD register may be read back from the TxC-
MD register.
the TxLength register.
122.
Table 3.19 on page
133.
Table 3.18.7 on
CS89712
DS502PP2