cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 112
cs89712
Manufacturer Part Number
cs89712
Description
High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS89712.pdf
(170 pages)
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Bit
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RCRS: Right Channel Receive FIFO Service Request (read-only)
0 — Right Channel Receive FIFO is less than half full (five or fewer entries filled) or DAI dis-
abled
1 — Right Channel Receive FIFO is half full or more (six or more entries filled) and DAI opera-
tion is enabled, interrupt request signaled if not masked (if RCRM = 1)
LCTS: Left Channel Transmit FIFO Service Request Flag (read-only)
0 — Left Channel Transmit FIFO is more than half full or less (four or fewer entries filled) or DAI
disabled.
1 — Left Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI opera-
tion is enabled, interrupt request signaled if not masked
(if LCTM = 1)
LCRS: 0 — Left Channel Receive FIFO is less than half full (five or fewer entries filled) or DAI
disabled.
1 — Left Channel Receive FIFO is half full or more (six or more entries filled) and DAI opera-
tion is enabled, interrupt request signalled if not masked (if LCRM = 1)
Right Channel Transmit FIFO Underrun
0 — Right Channel Transmit FIFO has not experienced an underrun
1 — Right Channel Transmit logic attempted to fetch data from transmit FIFO while it was
empty, request interrupt
RCRO: Right Channel Receive FIFO Overrun
0 — Right Channel Receive FIFO has not experienced an overrun
1 — Right Channel Receive logic attempted to place data into receive FIFO while it was full,
request interrupt
LCTU: Left Channel Transmit FIFO Underrun
0 — Left Channel Transmit FIFO has not experienced an underrun
1 — Left Channel Transmit logic attempted to fetch data from transmit FIFO while it was empty,
request interrupt
LCRO: Left Channel Receive FIFO Overrun
0 — Left Channel Receive FIFO has not experienced an overrun
1 — Left Channel Receive logic attempted to place data into receive FIFO while it was full,
request interrupt
RCNF: Right Channel Transmit FIFO Not Full (read-only)
0 — Right Channel Transmit FIFO is full
1 — Right Channel Transmit FIFO is not full
RCNE: Right Channel Receive FIFO Not Empty (read-only)
0 — Right Channel Receive FIFO is empty
1 — Right Channel Receive FIFO is not empty
LCNF: LCNETelecom Transmit FIFO Not Full (read-only)
0 — Left Channel Transmit FIFO is full
1 — Left Channel Transmit FIFO is not full
Table 62.
DAI
Control, Data and Status Register Locations (Continued)
Description
CS89712
DS502PP2
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