cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 34

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

ceive (SDIN) pins. This is synchronously con-
trolled by either the PLL or the external clock.
These fixed frequencies pass through a program-
mable divider network which will create the appro-
priate values for SCLK, LRCLK, and MCLK for
the desired sample frequency. Examples of sample
frequencies are shown in
DAI64Fs enables/disables the bit clock frequency
of 64 fs (and the other features as shown in
34
Note: To connect the port to any of the 4 features shown above, a minimum software configuration shown in the
Clock (MHz)
DAI –128 fs
Audio Bit
FEATURE
DAI-64 fs
1.0240
1.5360
2.8224
3.0720
4.0960
5,6448
6.1440
CODEC
1.4112
128 fs
table above must be observed. Each register column contains the bit name (bit #) that must be cleared or
set for each feature as shown in the column. This table does not complete the programming for each of the
features, but allows access to the port only. The interrupt masks for these features will have to be
programmed as well.
SSI2
Table 24. Relationship between Audio Clocks / Clock Source / Sample Frequencies
Clock (MHz)
Audio Bit
0.5120
0.7056
0.7680
1.4112
1.5360
2.0480
2.8224
3.0720
DAISEL[3] (H)
DAISEL[3] (H)
DAISEL[3] (L)
DAISEL[3] (L)
64 fs
128Fs[9] (H)
128Fs[9] (L)
SYSCON3
Table 23. Matrix for Programming the MUX
Table
Clock Source
11.2896
11.2896
11.2896
73.728
73.728
73.728
73.728
73.728
(MHz)
24. Register
DAIEN[16] (H)
DAIEN[16] (H)
DAIEN[16] (L)
DAIEN[16] (L)
DAIR (DAI)
Figure
Frequency (KHz)
Sample
22.025
11.025
7), but must be complemented by SYSCON3 bit 9
which will enable/disable 128 fs. To enable one
rate, you must disable the other.
2.17.2.2 DAI Frame Format
Each DAI frame is 128 bits long and comprises one
audio sample. Of this 128-bit frame, only 32 bits
are used for digital audio data. The remaining bits
are output as zeros. The LRCK signal is used as a
44.1
16
24
32
48
8
I2SF64[0] (H)
I2SF64[0] (L)
DAI64 fs
(X)
(X)
128 fs Divisor
(AUDDIV)
36
18
12
8
4
9
2
6
SERSEL[0] (H)
SERSEL[0] (L)
SYSCON2
(X)
(X)
64 fs Divisor
(AUDDIV)
CS89712
72
16
36
24
18
12
8
4
DS502PP2