cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 107

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.16.1 DAI Control Register (address 0x8000.2000)
DS502PP2
Reserved
31-24
24-31
0-15
Bit
15
16
17
18
19
20
21
22
23
7
The DAI control register (DAIR) contains eight different bit fields that control various functions within
the DAI interface.
Reserved
Reserved Must be set to 0x0404
Reserved
Reserved
DAIEN: DAI Interface Enable
0 — DAI operation disabled, control of the SDIN, SDOUT, SCLKLRCK, and LRCK pins given to
the SSI2 / CODEC / DAI pin mulitiplexing logic to assign I/O pins 60-64 to another block.
1 — DAI operation enabled
Note that by default, the SSI / CODEC have precedence over the DAI interface in regard to the
use of the I/O pins. Nevertheless, when bit 3 (DAISEL) of register SYSCON3 is set to 1, then
the above mentioned DAI ports are connected to I/O pins 60–64.
ECS: External Clock Select selects external MCLK when = 1.
ReservedMust be 0.
LCTM: Left Channel Transmit FIFO Interrupt Mask
0 — Left Channel Transmit FIFO half-full or less condition does not generate an interrupt (LCTS
bit ignored).
1 — Left Channel Transmit FIFO half-full or less condition generates an interrupt (state of LCTS
sent to interrupt controller).
LCRM: Left Channel Receive FIFO Interrupt Mask
0 — Left Channel Receive FIFO half-full or more condition does not generate an interrupt
(LCRS bit ignored).
1 — Left Channel Receive FIFO half-full or more condition generates an interrupt (state of
LCRS sent to interrupt controller).
RCTM: Right Channel Transmit FIFO Interrupt Mask
0 — Right Channel Transmit FIFO half-full or less condition does not generate an interrupt
(RCTS bit ignored).
1 — Right Channel Transmit FIFO half-full or less condition generates an interrupt (state of
RCTS sent to interrupt controller).
RCRM: Right Channel Receive FIFO Interrupt Mask
(RCRS bit ignored).
1 — Right Channel Receive FIFO half-full or more condition generates an interrupt (state of
RCRS sent to interrupt controller).
Reserved
Reserved
0 — Right Channel Receive FIFO half-full or more condition does not generate an interrupt
23
RCRM
22
RCTM
21
Table 58. DAI Control Register
LCRM
20
Description
LCTM
19
Reserved
18
ECS
17
DAIEN
16
CS89712
Reserved
15-0
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