cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 143

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

DS502PP2
Keyboard and
Buzzer drive
LED Flasher
Purpose I/O
Function
Interfaces
Boundary
IrDA and
General
RS232
Drives
PWM
Scan
LCD
Test
PB[0]/PRDY1
PB[1]/PRDY2
BOOTSEL[0]
BOOTSEL[1]
DRIVE[0:1]
nTEST[0:1]
LEDFLSH
LEDDRV
RXD[1-2]
COL[0-7]
TXD[1-2]
DD[0-3]
Signal
PD[0:7]
PA[0:7]
FB[0:1]
nTRST
PHDIN
PB[2:7]
PD[0]/
Name
PE[0]/
PE[1]/
TCLK
CL[1]
CL[2]
PE[2]
DSR
DCD
FRM
TDO
TMS
CTS
BUZ
TDI
M
Table 90. External Signal Functions (Continued)
D3, C3
M4, H3
M9, P7
L4, G5
B3, A3
L9, L7
K6, J9
M15
M2
M5
K4
N1
C4
E5
D4
E4
R8
R4
G4
L3
L5
T2
T8
J7
J8
J4
,
Signal
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Infrared LED drive output (UART1)
Photo diode input (UART1)
RS232 UART1 and 2 TX outputs
RS232 UART1 and 2 RX inputs
RS232 DSR input
RS232 DCD input
RS232 CTS input
LCD serial display data; pins can be used on power up to read
the ID of some LCD modules (See
LCD line clock
LCD pixel clock
LCD frame synchronization pulse output
LCD AC bias drive
Keyboard column drives (SYSCON1)
Buzzer drive output (SYSCON1)
LED flasher driver — multiplexed with Port D bit 0. This pin can pro-
vide up to 4 mA of drive current.
Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY
input); also used as keyboard row inputs
Port B I/O. All eight Port B bits can be used as GPIOs.
When the PC CARD1 or 2 control bits in the SYSCON2 register are
de-asserted, PB[0] and PB[1] are available for GPIO. When
asserted, these port bits are used as the PRDY signals for connected
CL-PS6700 PC Card Host Adapter devices.
Port D I/O
Port E I/O (3 bits only). Can be used as general purpose I/O during
normal operation.
During power-on reset, PE[0] and PE[1] are inputs and are latched by
the rising edge of nPOR to select the memory width that the CS89712
will use to read from the boot code storage device (i.e., external 8-bit-
wide FLASH bank).
During power-on reset, PE[2] is latched by the rising edge of nPOR to
enable the PLL clocking mode.
PWM drive outputs. These pins are inputs on power up to determine
what polarity the output of the PWM should be when active. Other-
wise, these pins are always an output (See
PWM feedback inputs
JTAG data in
JTAG data out
JTAG mode select
JTAG clock
JTAG async reset
Test mode select inputs are used in conjunction with the power-on
latched state of nURESET to select the various device test modes.
Description
Figure
Table
31).
91).
CS89712
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