cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 154

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

154
nEXPRDY
Notes: 1. tnCSWR = 35 nsec at 36.864 MHz, 70 ns at 18.432 MHz
nCS[5:0]
eXPCLK
D[31:0]
A[27:0]
WORD
nMWE
2. Consecutive reads with sequential access enabled are identical except that the sequential access
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 nsec at 36 MHz or 54 nsec at 18.432 MHz), by either driving EXPRDY low and/or
by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK
before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown
for clarity.
wait state field is used to determine the number of wait states, and no idle cycles are inserted
between successive non-sequential ROM/expansion cycles. This improves performance so the
SQAEN bit should always be set where possible.
this cannot be driven with valid timing under zero wait state conditions.
Bus held
Figure 26. Consecutive Memory Write Cycles with Minimum Wait States
t2
Write data
t8
tnCSWR
t5
t6
t7
t2
Write data
tADWR
CS89712
DS502PP2