cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 111

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.16.6 DAISR DAI Status (address 0x8000.2100)
DS502PP2
RCNFLCTU
16-20
21-31
0-14
Reserved
Bit
15
Bit
31-13
0
6
FIFO operation complete bit (FIFO) is set in the DAI status register before writing another value to this
register.
The DAI Status register (DAISR) contains bits which signal FIFO overrun and underrun errors and
FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.
The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty,
when a FIFO operation is complete, and when the right channel or left channel portion of the CODEC
is enabled (no interrupt generated).
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read / write bits are called status bits, read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ-
ing a one to a sticky status bit clears it, while writing a zero has no effect. Read-only flags are set and
cleared by hardware, and writes have no effect. Additionally, some bits which cause interrupts have
corresponding mask bits in the control register and are indicated in the section headings below. Note
that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con-
troller mask register INTMR3.
Reserved
FIFOEN: FIFO Transmit Bit
0 — Disable Transmit
1 — Enable Transmit
FIFO CHANNEL SELECT:
01101b — Left channel select
10001b — Right channel select
Reserved
RCTS: Right Channel Transmit FIFO Service Request Flag (read-only)
0 — Right Channel Transmit FIFO is more than half full (five or more entries filled) or DAI dis-
abled
1 — Right Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI oper-
ation is enabled, interrupt request signaled if not masked
(if RCTM = 1)
LCRORCRO
FIFO
12
5
Table 62.
DAI
LCTURCTU
LCNE
Table 61. DAI Data Register 2
Control, Data and Status Register Locations
11
4
LCRS
LCNF
Description
Description
10
3
RCNE
LCTS
9
2
LCRSRCRS
RCNF
8
1
CS89712
RCCELCRO
LCTSRCTS
7
0
111