cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 44

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

Snooze State these are the only peripherals apart
from the LCD controller and on-chip SRAM to re-
main enabled. If either or both of the converters are
not required, they should be switched off before en-
tering Snooze State to save power. PWMs are dis-
abled by writing zeros into the drive ratio fields in
the PMPCON Pump Control register.
Note:
2.23 Ethernet Port Overview
The Ethernet port provides a flexible set of perfor-
mance features and configuration options, allowing
designers to develop Ethernet circuits that meet
their system requirements.
The Ethernet Port performs two basic functions:
Ethernet packet transmission and reception. Before
transmission or reception is possible, the Ethernet
Port must be configured.
2.23.1 Configuration
The Ethernet port must be configured for packet
transmission and reception at power-up or reset.
Parameters must be written to its internal Configu-
ration and Control registers. Configuration data can
either be written to the Ethernet port by software or
loaded automatically from an external EEPROM.
Section 2.24, “Programming the EEPROM” and
Section 2.6, “Ethernet EEPROM Configurations”
describe the configuration process in detail. Sec-
tion 3.2.3, “Ethernet Status/Control Registers”
provides a detailed description of the bits in the
Configuration and Control Registers.
2.23.2 Packet Transmission
Packet transmission occurs in two phases. In the
first phase, the Ethernet frame is moved into the
Ethernet port’s buffer memory. The first phase be-
gins with the issuance of a Transmit Command.
This informs the Ethernet port both that a frame is
44
To maximize power savings, the drive ratio
fields should be used to disable the PWMs,
instead of the FB pins. The clocks that source
the PWMs are disabled when the drive ratio
fields are zeroed.
to be transmitted and when to start transmission
(i.e. after 5, 381, 1021 or all bytes have been trans-
ferred). Following the Transmit Command is the
Transmit Length, indicating how much buffer
space is required. When buffer space is available,
the Ethernet frame is written into the Ethernet
port’s internal memory.
In the second phase of transmission, the Ethernet
port converts the frame into an Ethernet packet then
transmits it onto the network. The second phase be-
gins with the Ethernet port transmitting the pream-
ble and Start-of-Frame delimiter as soon as the
proper number of bytes has been transferred into its
transmit buffer (5, 381, 1021 bytes or full frame,
depending on configuration). The preamble and
Start-of-Frame delimiter are followed by the Desti-
nation Address, Source Address, Length field and
LLC data (all software supplied). If the frame is
less than 64 bytes, including CRC, the Ethernet
port adds pad bits if so configured. Finally, the
Ethernet port appends the proper 32-bit CRC value.
Section 2.34, “Transmit Operation” provides a de-
tailed description of packet transmission.
2.23.3 Packet Reception
Like packet transmission, packet reception occurs
in two phases. In the first phase, the Ethernet port
receives an Ethernet packet and stores it in on-chip
memory. The first phase of packet reception begins
with the receive frame passing through the analog
front end and Manchester decoder where Manches-
ter data is converted to NRZ data. Next, the pream-
ble and Start-of-Frame delimiter are stripped off
and the receive frame is sent through the address
filter. If the frame’s Destination Address matches
the criteria programmed into the address filter, the
packet is stored in the Ethernet port’s internal
memory. The Ethernet port then checks the CRC,
and depending on the configuration, informs the
processor that a frame has been received. In the
second phase, the receive frame is transferred into
host memory.
CS89712
DS502PP2