cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 153

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

DS502PP2
Notes:
EXPRDY
nCS[5:0]
EXPCLK
WORD
D[31:0]
A[27:4]
nMOE
A[3:0]
2. Consecutive reads with sequential access enabled are identical except that the sequential access
1.tEXBST = 35 ns at 36.864 MHz
35 ns at 18.432 MHz
(Value for 36.864 MHz assumes 1 wait state.)
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 nsec at 36 MHz or 54 nsec at 18.432 MHz), by either driving EXPRDY low and/or
by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before
the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is
sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
wait state field is used to determine the number of wait states, and no idle cycles are inserted
between successive non-sequential ROM/expansion cycles. This improves performance so the
SQAEN bit should always be set where possible.
Bus held
Figure 25. Sequential Page Mode Read Cycles with Minimum Wait States
t1
0
tEXRD
t5
t6
Data in
t3
t4
tEXBST
4
t3
Data in
t4
8
tEXBST
Data in
t3
CS89712
t4
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