cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 155

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

DS502PP2
nCAS / nWE
(prech sel)
nRAS /
Bank sel
1. tRCD (delay time ACT to READ/WRITE command) = 30 ns or 2 cycles at 36 MHz.
2. tRP (PRE to ACT command period) = 30 ns or 2 cycles at 36 MHz.
3. tRAS (ACT to PRE command period) = 60 ns or 3 cycles at 36 MHz.
4. tRC (ACT to REF/ACT command period [operation]) = 90 ns or 4 cycles at 36 MHz.
5. For SDCAS latency 3, there will be an extra cycle between T4 and T5.
6. For CAS latency 3, there will be an extra cycle between T4 and T5.
DQM
CLK
CKE
addr
nCS
A10
DQ
NOP
T0
1 dev
ACT
bank
row
row
Figure 27. SDRAM Read Cycles CAS Latency = 2
T1
tRCD
NOP
T2
1 dev
READ NOP
bank
col
T3
CAS lat 2
tRAS
T4
NOP
DI0
T5
tRC
NOP
DI1
T6
NOP
DI2
auto precharge
T7
NOP
DI3
T8
tRP
NOP
T9
NOP
T10
(ACT)
CS89712
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