cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 141

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

5.2 External Signal Functions
DS502PP2
Address bus
Function
Interrupts
Data bus
Interface
Memory
BA[0-1]/A[13/14]
Ethernet Enable
nMOE/nSDCAS
nMWE/nSDWE
HALFWORD
nMEDCHG/
SDQM[2-3]
nCS[0-1, 3]
SDCS[0-1]
nEINT[1:2]
DRA[0-14]
nEXTFIQ
EXPRDY
nCS[4-5]
EXPCLK
A[13-27]
nBROM
SDCKE
WORD/
Signal
D[0-31]
SDCLK
A[0-14]
WRITE
/ nCS2
Name
A1, B1,
C2, B2
N2, P1
A2, E3
D1, F2
G12,
D16
E10
H13
T15
J12
E2
D2
C1
G3
G1
E1
N4
F1
Table 90. External Signal Functions
Signal
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
32-bit system data bus for memory, DRAM, and I/O interface
15 bits of system byte address during memory and expansion cycles
DRA[0-14] is multiplexed with A[13-27], offering additional power sav-
ings since the lightest loading is expected on the high order ROM
address lines.
Whenever the CS89712 is in the Standby State, the external address
and data buses are driven low. The RUN signal is used internally to
force these buses to be driven low. This is done to prevent peripher-
als that are powered-down from draining current. Also, the internal
peripheral’s signals get set to their Reset State.
SDRAM bank select pins.
SDRAM chip selects.
SDRAM clock.
SDRAM clock enable.
SDRAM byte masks. SDQM0-1 are muxed with Port D data pins.
Memory output enable/SDRAM CAS control signal
Memory write enable/SDRAM write enable control signal
Chip select; active low, SRAM-like chip selects for expansion
Chip select; active low, indicates either Ethernet port or CS2 expan-
sion range activity. Pins G12 and H13 must be tied together.
Chip select; active low, CS for expansion or for CL-PS6700 select
Expansion port ready; external expansion devices drive this low to
extend the bus cycle. This is used to insert wait states for an external
bus cycle.
Write strobe, low during reads, high during writes from the CS89712
To do write accesses of different sizes Word and Half-Word must be
externally decoded. The encoding of these signals is as follows:
Expansion clock rate is the same as the CPU clock for 18 MHz. It
runs at 36.864 MHz for 36,49 and 74 MHz modes.
Media changed input; active low, deglitched. Used as a general pur-
pose FIQ interrupt during normal operation. It is also used on power
up to configure the processor to either boot from the internal Boot
ROM, or from external memory. When low, the chip will boot from the
internal Boot ROM.
External active low fast interrupt request input
Two general purpose, active low interrupt inputs
Access Size
Half-Word
Word
Byte
Word
1
0
*
Description
Half-Word
0
0
1
CS89712
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