cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 114

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.16.6.5 Right Channel Transmit FIFO Underrun Status (RCTU)
3.16.6.6 Right Channel Receive FIFO Overrun Status (RCRO)
3.16.6.7 Left Channel Transmit FIFO Underrun Status (LCTU)
3.16.6.8 Left Channel Receive FIFO Overrun Status (LCRO)
3.16.6.9 Right Channel Transmit FIFO Not Full Flag (RCNF)
3.16.6.10 Right Channel Receive FIFO Not Empty Flag (RCNE)
3.16.6.11 Left Channel Transmit FIFO Not Full Flag (LCNF)
3.16.6.12 Left Channel Receive FIFO Not Empty Flag (LCNE)
114
vice request and / or interrupt) is automatically cleared.
This is set when the Right Channel Transmit logic attempts to fetch data from the FIFO after it has
been emptied. When an underrun occurs, the Right Channel Transmit logic continuously transmits
the last valid right channel value which was transmitted before the underrun. Once data is placed in
the FIFO and it is transferred down to the bottom, the Right Channel Transmit logic uses the new val-
ue within the FIFO for transmission. When the RCTU bit is set, an interrupt request is made.
This is set when the right channel receive logic attempts to place data into the Right Channel Receive
FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to
the RCRO status bit is asserted, and the newly received data is discarded. This process is repeated
for each new sample received until at least one empty FIFO entry exists. When this bit is set, an in-
terrupt request is made.
The Left Channel Transmit FIFO Underrun Status Bit (LCTU) is set when the Left Channel Transmit logic at-
tempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the Left
Channel Transmit logic continuously transmits the last valid left channel value which was transmitted before
the underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the Left Channel
Transmit logic uses the new value within the FIFO for transmission. When the LCTU bit is set, an interrupt re-
quest is made.
The Left Channel Receive FIFO Overrun Status Bit (LCRO) is set when the Left Channel Receive log-
ic places data into the Left Channel Receive FIFO after it has been completely filled. Each time a new
piece of data is received, the set signal to the LCRO status bit is asserted, and the newly received
sample is discarded. This process is repeated for each new piece of data received until at least one
empty FIFO entry exists. When the LCRO bit is set, an interrupt request is made.
The Right Channel Transmit FIFO Not Full Flag (RCNF) is a read-only bit which is set whenever the
Right Channel Transmit FIFO contains one or more entries which do not contain valid data and is
cleared when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the
Right Channel Transmit FIFO. This bit does not request an interrupt.
The Right Channel Receive FIFO Not Empty Flag (RCNELCNF) is a read-only bit which is set when
ever the Right Channel Receive FIFO contains one or more entries of valid data and is cleared when
it no longer contains any valid data. This bit can be polled when using programmed I/O to remove
remaining data from the receive FIFO. This bit does not request an interrupt.
This is a read-only bit which is set when ever the Left Channel Transmit FIFO contains one or more
entries which do not contain valid data. It is cleared when the FIFO is full. This bit can be polled when
using programmed I/O to fill the Left Channel Transmit FIFO. This bit does not request an interrupt.
This is a read-only bit set when the Left Channel Receive FIFO contains one or more entries of valid
CS89712
DS502PP2