cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 85

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.5.3
This register allows additional control for the CS89712. The bits of this register are defined in
DS502PP2
0
1:2
3
4
5:7
8
9
10
VERSN[2]
Reserved
Reserved
15
7
Bit
SYSCON3 System Control Register 3 (address 0x8000.2200)
VERSN[1]
ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be
used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte
SYNCIO(7:0) only is used for compatibility with the CL-PS7111. When this bit = 1, the ADC Con-
figuration Extension field in the SYNCIO register is used for ADC Configuration data and the
value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit).
CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling.
The table below lists the available options.
Note: To determine the number of wait states programmed refer to
DAISEL: When set selects the DAI Interface. When cleared selects either the SSI or telephony
codec interface (i.e., DAISEL bit is default low).
ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the
ADCCLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the
opposite edges are used.
VERSN[0:2]: Additional read-only version bits — will read ‘000’
Reserved. This bit must be set to zero
128Fs: When set, this selects the 128 fs mode. Cleared by default to enable 64 fs operation.
ENPD67: Pd[6-7] control the byte mask of the SDRAM interface. Setting of this bit allows their
use as GPIO bits for applications not using SDRAM.
Reserved
Reserved
CLKCTL(1:0)
14
6
Value
no circumstances should the CLKCTL bits be changed using a buffered write.
00
01
10
11
VERSN[0]
Reserved
Reserved
13
5
18.432 MHz
36.864 MHz
49.152 MHz
73.728 MHz
Frequency
Processor
ADCCKNSEN
Reserved
Table 39. SYSCON3
12
4
Description
Reserved
Memory Bus
DAISEL
18.432 MHz
36.864 MHz
36.864 MHz
36.864 MHz
Frequency
11
3
CLKCTL1
ENPD67
10
2
Wait State Scaling
Table 46
CLKCTL0
1
2
2
2
128Fs
9
1
and
Table
Table
CS89712
38.
FASTWAKE
ADCCON
47. Under
8
0
85