cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 93

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.7.2
The Memory Configuration Register 2 is a 32-bit read / write register which sets the configuration of the two expan-
sion and ROM selects nCS[4:5]. Each select is configured with a 1-byte field starting with expansion select 4.
Each of the six non-reserved byte fields for chip select configuration in the memory configuration registers are iden-
tical and define the number of wait states, the bus width, enable EXPCLK output during accesses and enable se-
quential mode access. This byte field is defined below. This arrangement applies to nCS[0:3], and nCS[4:5] when
the PC CARD enable bits in the SYSCON2 register are not set. The state of these bits is ignored for the Boot ROM
and local SRAM fields in the MEMCFG2 register.
Table 45
be read in the SYSFLG1 register. All bits in the memory configuration register are cleared by a system reset, and
the state of the BOOTBIT bits are determined by Port E bits 0 and 1 on the CS89712 during power-on reset. The
state of PE[1] and PE[0] determine whether the CS89712 is going to boot from either 32-bit-wide, 16-bit-wide or 8-
bit-wide ROMs.
Table 46
rate, the encoding becomes more complex.
ing the previously unused bit combinations to specify more variations of random and sequential wait states.
Note: See AC Characteristics for more detail on bus timing.
The memory area decoded by CS[6] is reserved for the on-chip SRAM, hence this does not require a configuration
field in MEMCFG2. It is automatically set up for 32-bit-wide, no-wait-state accesses. For the Boot ROM, it is auto-
matically set up for 8-bit, no wait state accesses.
Chip selects nCS[4] and nCS[5] are used to select two CL-PS6700 PC CARD controller devices. These have a mul-
tiplexed 16-bit wide address / data interface, and the configuration bytes in the MEMCFG2 register have no meaning
when these interfaces are enabled.
DS502PP2
Bus Width Field
(Boot ROM)
CLKENB
31:24
00
01
10
11
00
01
10
11
00
01
10
11
defines the bus width field. Note that the effect of this field is dependent on the two BOOTBIT bits that can
shows the values for the wait states for random and sequential wait states at 18 MHz bus. At 36 MHz bus
MEMCFG2 Memory Configuration Register 2 (address 0x8000.01C0)
7
BOOTBIT1
0
0
0
0
0
0
0
0
1
1
1
1
(Local SRAM)
SQAEN
23:16
6
BOOTBIT0
Table 45. Values of the Bus Width Field
0
0
0
0
1
1
1
1
0
0
0
0
Table 47
Expansion Transfer Mode
preserves compatibility with the previous devices, while allow-
nCS[5] configuration
32-bit wide bus access
16-bit wide bus access
32-bit wide bus access
16-bit wide bus access
16-bit wide bus access
32-bit wide bus access
8-bit wide bus access
8-bit wide bus access
8-bit wide bus access
Wait States Field
Reserved
Reserved
Reserved
15:8
5:2
Port E bits 1,0 during
nCS[4] configuration
NPOR reset
High, Low
Low, High
Low, High
Low, High
Low, High
High, Low
High, Low
High, Low
Bus width
Low, Low
Low, Low
Low, Low
Low, Low
7:0
1:0
CS89712
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