cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 16

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

cleared if a checksum error is detected. In this case,
the Ethernet port performs a partial reset and is re-
stored to its default. Once initialization is complete
(configuration loaded from EEPROM or reset to
default configuration) the INITD bit (SelfST regis-
ter, bit 7) is set .
2.7 Clocks
The clock source is the on-chip PLL, enabled by
strapping Port E pin 2 (PE[2]) low. This pin’s state
is latched at the rising edge of nPOR (power-up).
After power-up, PE[2] can be used as a GPIO.
The CS89712 contains several separate sections of
logic, each clocked according to its own clock fre-
quency requirements. See each peripheral device
section for more details. The section below de-
scribes the clocking for both the ARM720T and ad-
dress/data bus.
2.7.1
The ARM720T clock can be programmed to
18.432 MHz,
73.728 MHz with the PLL running at 147456 MHz,
twice the highest possible CPU clock frequency.
The PLL uses an external 3.6864 MHz crystal. By
default, the address/data buses run at 18.432 MHz.
When the clock frequency is selected to be
36 MHz, both the ARM720T and the address/data
buses are clocked at 36 MHz. When the clock fre-
quency is selected higher than 36 MHz, only the
ARM720T gets clocked at this higher speed. The
address/data will be fixed at 36 MHz. The clock
frequency used is selected by programming the
CLKCTL[1:0] bits in the SYSCON3 register. The
clock frequency selection does not effect the EPB
(external peripheral bus). Therefore, all the periph-
16
On-Chip PLL
36.864 MHz,
49.152 MHz,
or
eral clocks are fixed, regardless of the clock speed
selected for the ARM720T.
Note:
2.7.1.1
When connecting a crystal to the on-chip PLL in-
terface pins (i.e. MOSCIN and MOSCOUT), the
crystal and circuit should conform to the following
requirements:
•
•
•
•
Alternatively, a digital clock source can be used to
drive the MOSCIN pin of the CS89712. With this
approach, the voltage levels of the clock source
should match that of the V
CS89712’s pads (i.e. the supply voltage level used
to drive all of the non-V
CS89712). The output clock pin (i.e., MOSCOUT)
should be left floating.
A 3.6864 MHz fundamental mode crystal
should be used.
A start-up resistor is not necessary, since one is
provided internally.
Start-up loading capacitors may be placed on
each side of the external crystal and ground.
Their value should be in the range of 10 pF.
However, their values should be selected based
upon the crystal specifications. The total sum of
the capacitance of the traces between the
CS89712’s clock pins, the capacitors, and the
crystal leads should be subtracted from the
crystal’s specifications when determining the
values for the loading capacitors.
The crystal frequency drift should be less than
100 ppm over the operating temperature range.
After modifying the CLKCTL[1:0] bits, the next
instruction should always be a ‘NOP’.
Characteristics of the PLL Interface
DD
DD
core pins on the
supply for the
CS89712
DS502PP2